Dual-Loop Gate Drivers with Analog and Digital Slope Shaping

Abstract

Setting the values of the switching transients (dVCE/dt and dIC/dt) has become more and more important especially for modern power semiconductor technologies, like insulated gate bipolar transistors (IGBTs) in the newest trench-/fieldstop technologies, Superjunction MOSFETs or silicon carbide (SiC). The extremely fast switching speeds of these devices have led to switching losses of almost close to zero, but has also complicated the control of voltage and current spikes or electromagnetic compatibility (EMC) in switched applications like motor drives, switched-mode power supplies (SMPS) and power factor correction (PFC) stages. The focus of this work is on a new hardware concept for an active gate driver that is capable of flexible switching behavior optimization by using a dual-loop approach. This enables regulated dVCE/dt and dIC/dt transients to be optimal for specific application requirements. Conventional gate drivers, as used in most commercial products, are commonly designed in passive architectures and are therefore unsuitable for an effective and flexible optimization of the switching behavior, due to their limited capabilities to influence the switching transients (dVCE/dt and dIC/dt). Closed-loop gate drivers offer a sophisticated approach to achieve a desired trade-off between switching losses, delay, EMC and safe operating area (SOA) and can be realized in the analog or in the digital domain. The dual-loop design adressed in this work comprises both analog and digital closed-loop control on dVCE/dt and dIC/dt. Hence, it combines high speed and linearity of a closed-loop analog gate driver, that is able to perform continous-time regulation, with the advantages of adaptive digital control, like flexibility and parameter independency. As the analog loop is the critical element, setting the dynamics and stability of the system, it is modeled and analyzed in the small-signal domain with focus on non-linearity of parameters and operating point dependencies. The model parameters are extracted from experimental data for an IGBT and a Superjunction MOSFET. Major parameters of influence, such as gate resistor and the capacitance in the summing node, are investigated to achieve stable control. Another important detail is the sensing of dVCE/dt and dIC/dt to generate input data for the signal processing blocks of the digital loop. This guarantees for accurate interaction between the analog and the digital loop. The sensing blocks are optimized for accuracy and bandwidth. Different circuit concepts for the gate driver are evaluated and the full system is designed in hardware. Experimental results show that the combination of a digital and an analog loop increases the accuracy of the dVCE/dt and dIC/dt control compared to a pure analog loop system by more than 10%, independent of the actual device technology utilized. Precise slew rate control is demonstrated for IGBT, Superjunction MOSFET and SiC. Due to the device-independency, the gate driver enables the flexible use of different device technologies in a given application. The more accurate control helps to control voltage and current overshoots. In motor drives, the control of dVCE/dt helps to protect the motor from destruction and therefore increases the lifetimes.