dc.identifier.uri |
http://dx.doi.org/10.15488/1473 |
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dc.identifier.uri |
http://www.repo.uni-hannover.de/handle/123456789/1498 |
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dc.contributor.author |
Anders, J.
|
|
dc.contributor.author |
Mathis, Wolfgang
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|
dc.contributor.author |
Ortmanns, M.
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dc.date.accessioned |
2017-05-10T11:33:54Z |
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dc.date.available |
2017-05-10T11:33:54Z |
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dc.date.issued |
2007 |
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dc.identifier.citation |
Anders, J.; Mathis, W.; Ortmanns, M.: Entwurf von zeitkontinuierlichen Σ Δ-Modulatoren - Äquivalenz zwischen zeitkontinuierlichen und zeitdiskreten Systemen [Design of continuous-time ΣΔ-modulators - Equivalence between continuous-time and discrete-time systems]. In: Advances in Radio Science 5 (2007), S. 221-224. DOI: https://doi.org/10.5194/ars-5-221-2007 |
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dc.description.abstract |
In the article at hand a complete equivalency, i.e. including the input signal, between continuous-time and discrete-time Σ Δ-modulators in state-space is derived. In addition, it is shown, how one can incorporate the important non-ideality of "excess loop delay" into the formalism. The method introduced is supposed to facilitate the design, especially the stability analysis part of the design, of continuoustime Σ Δs by making use of the empirically thoroughly examined discrete-time systems. |
eng |
dc.description.abstract |
Im vorliegenden Artikel wird eine vollstängige, d.h. unter Einbeziehung des Eingangssignals, Äquivalenz zwischen zeitkontinuierlichen und zeitdiskreten ΣΔ-Modulatoren im Zustandsraum hergeleitet. Es wird ebenfalls gezeigt, wie eine wichtige Nichtidealität, das sog. "excess loop delay", in den Berechnungen berücksichtigt werden kann. Die dargestellte Methode dient dazu, den Entwurf und dabei vor allem die Stabilitätsuntersuchungen, von zeitkontinuierlichen ΣΔs auf die bereits empirisch intensiv erforschten zeitdiskreten Systeme zurückzuführen. |
ger |
dc.language.iso |
ger |
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dc.publisher |
Göttingen : Copernicus GmbH |
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dc.relation.ispartofseries |
Advances in Radio Science 5 (2007) |
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dc.rights |
CC BY-NC-SA 2.5 Unported |
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dc.rights.uri |
https://creativecommons.org/licenses/by-nc-sa/2.5/ |
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dc.subject |
Continuous-time |
eng |
dc.subject |
Discrete time system |
eng |
dc.subject |
Excess loop delay |
eng |
dc.subject |
Nonideality |
eng |
dc.subject |
Stability analysis |
eng |
dc.subject |
Continuous time systems |
eng |
dc.subject |
Design |
eng |
dc.subject |
Digital control systems |
eng |
dc.subject |
Modulators |
eng |
dc.subject |
Discrete time control systems |
eng |
dc.subject.ddc |
621,3 | Elektrotechnik, Elektronik
|
ger |
dc.title |
Entwurf von zeitkontinuierlichen Σ Δ-Modulatoren - Äquivalenz zwischen zeitkontinuierlichen und zeitdiskreten Systemen [Design of continuous-time ΣΔ-modulators - Equivalence between continuous-time and discrete-time systems] |
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dc.type |
Article |
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dc.type |
Text |
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dc.relation.issn |
1684-9965 |
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dc.relation.doi |
https://doi.org/10.5194/ars-5-221-2007 |
|
dc.bibliographicCitation.volume |
5 |
|
dc.bibliographicCitation.firstPage |
221 |
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dc.bibliographicCitation.lastPage |
224 |
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dc.description.version |
publishedVersion |
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tib.accessRights |
frei zug�nglich |
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