Zusammenfassung: | |
Purpose: This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very-large-scale integration (VLSI) circuits. Design/methodology/approach: The parasitic effects are modelled by large RLC networks and current sources for the digital switching currents. Based on the determined behaviour of the digital modules, an efficient description of these networks is proposed, which allows for a more efficient model reduction than standard methods. Findings: The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally, an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources is presented. Practical implications: The presented method can be applied to large electrical networks, used in the modelling of parasitic effects, for reducing their size. A reduced model is created which can be used in investigations with circuit simulators requiring a lowered computational effort. Originality/value: Contrary to existing methods, the presented method includes the knowledge of the behaviour of the sources in the model to enhance the model reduction process. © Emerald Group Publishing Limited 0332-1649.
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Lizenzbestimmungen: | Es gilt deutsches Urheberrecht. Das Dokument darf zum eigenen Gebrauch kostenfrei genutzt, aber nicht im Internet bereitgestellt oder an Außenstehende weitergegeben werden. Dieser Beitrag ist aufgrund einer (DFG-geförderten) Allianz- bzw. Nationallizenz frei zugänglich. |
Publikationstyp: | Article |
Publikationsstatus: | publishedVersion |
Erstveröffentlichung: | 2011 |
Schlagwörter (englisch): | Circuits, Modelling, Circuit simulators, Computational effort, Current sources, Design/methodology/approach, Digital switching, Efficient simulation, Electrical networks, Mixed signal, Model reduction, Modelling, Parasitic couplings, Parasitic effect, Reduced model, Reduction method, RLC networks, Standard method, Supply voltages, Very-large-scale integration circuits, Networks (circuits), VLSI circuits |
Fachliche Zuordnung (DDC): | 620 | Ingenieurwissenschaften und Maschinenbau, 510 | Mathematik |
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