Stepwise transformation of algorithms into array processor architectures by the decomp

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dc.identifier.uri http://dx.doi.org/10.15488/2020
dc.identifier.uri http://www.repo.uni-hannover.de/handle/123456789/2045
dc.contributor.author Vehlies, U.
dc.date.accessioned 2017-10-10T08:43:52Z
dc.date.available 2017-10-10T08:43:52Z
dc.date.issued 1995
dc.identifier.citation Vehlies, U.: Stepwise transformation of algorithms into array processor architectures by the decomp. In: Vlsi Design 3 (1995), Nr. 1, S. 67-80. DOI: https://doi.org/10.1155/1995/76861
dc.description.abstract A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems. eng
dc.language.iso eng
dc.publisher Reading : Gordon Breach Sci. Publ. Ltd.
dc.publisher New York, NY : Hindawi Publishing Corporation
dc.relation.ispartofseries Vlsi Design 3 (1995), Nr. 1
dc.rights CC BY 3.0 Unported
dc.rights.uri https://creativecommons.org/licenses/by/3.0/
dc.subject computer aided synthesis eng
dc.subject synthesis algorithms eng
dc.subject cad for architecture design eng
dc.subject stepwise transformation eng
dc.subject mapping methodology eng
dc.subject data independent algorithms eng
dc.subject run time protocol eng
dc.subject nonregular dependence graphs eng
dc.subject array processor architectures eng
dc.subject.ddc 621,3 | Elektrotechnik, Elektronik ger
dc.title Stepwise transformation of algorithms into array processor architectures by the decomp eng
dc.type article
dc.type Text
dc.relation.issn 1065-514X
dc.relation.doi https://doi.org/10.1155/1995/76861
dc.bibliographicCitation.issue 1
dc.bibliographicCitation.volume 3
dc.bibliographicCitation.firstPage 67
dc.bibliographicCitation.lastPage 80
dc.description.version publishedVersion
tib.accessRights frei zug�nglich


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