dc.identifier.uri |
http://dx.doi.org/10.15488/1212 |
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dc.identifier.uri |
http://www.repo.uni-hannover.de/handle/123456789/1236 |
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dc.contributor.author |
Lück, Martin
|
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dc.contributor.author |
Meier, Arne
|
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dc.contributor.author |
Schindler, Irena
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dc.date.accessioned |
2017-03-20T13:19:20Z |
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dc.date.available |
2017-03-20T13:19:20Z |
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dc.date.issued |
2017 |
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dc.identifier.citation |
Luck, M.; Meier, A.; Schindler, I.: Parametrised complexity of satisfiability in temporal logic. In: ACM Transactions on Computational Logic 18 (2017), Nr. 1, 1. DOI: https://doi.org/10.1145/3001835 |
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dc.description.abstract |
We apply the concept of formula treewidth and pathwidth to computation tree logic, linear temporal logic, and the full branching time logic. Several representations of formulas as graphlike structures are discussed, and corresponding notions of treewidth and pathwidth are introduced. As an application for such structures, we present a classification in terms of parametrised complexity of the satisfiability problem, where we make use of Courcelle's famous theorem for recognition of certain classes of structures. Our classification shows a dichotomy between W[1]-hard and fixed-parameter tractable operator fragments almost independently of the chosen graph representation. The only fragments that are proven to be fixed-parameter tractable (FPT) are those that are restricted to the X operator. By investigating Boolean operator fragments in the sense of Post's lattice, we achieve the same complexity as in the unrestricted case if the set of available Boolean functions can express the function "negation of the implication." Conversely, we show containment in FPT for almost all other clones. © ACM 2017. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in ACM Transactions on Computational Logic 18 (2017), Nr. 1, 1. DOI: https://doi.org/10.1145/3001835. |
eng |
dc.description.sponsorship |
DFG/ME 4279/1-1 |
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dc.language.iso |
eng |
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dc.publisher |
Association for Computing Machinery |
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dc.relation.ispartofseries |
ACM Transactions on Computational Logic 18 (2017), Nr. 1 |
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dc.rights |
Es gilt deutsches Urheberrecht. Das Dokument darf zum eigenen Gebrauch kostenfrei genutzt, aber nicht im Internet bereitgestellt oder an Außenstehende weitergegeben werden. |
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dc.subject |
Computation tree logic |
eng |
dc.subject |
Linear temporal logic |
eng |
dc.subject |
Parametrised complexity |
eng |
dc.subject |
Pathwidth |
eng |
dc.subject |
Post's lattice |
eng |
dc.subject |
Temporal depth |
eng |
dc.subject |
Temporal logic |
eng |
dc.subject |
Treewidth |
eng |
dc.subject |
Boolean functions |
eng |
dc.subject |
Formal logic |
eng |
dc.subject |
Temporal logic |
eng |
dc.subject |
Computation tree logic |
eng |
dc.subject |
Linear temporal logic |
eng |
dc.subject |
Parametrised complexity |
eng |
dc.subject |
Pathwidth |
eng |
dc.subject |
Post's lattice |
eng |
dc.subject |
Temporal depth |
eng |
dc.subject |
Tree-width |
eng |
dc.subject |
Computer circuits |
eng |
dc.subject.ddc |
510 | Mathematik
|
ger |
dc.title |
Parametrised complexity of satisfiability in temporal logic |
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dc.type |
Article |
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dc.type |
Text |
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dc.relation.issn |
1529-3785 |
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dc.relation.doi |
https://doi.org/10.1145/3001835 |
|
dc.bibliographicCitation.issue |
1 |
|
dc.bibliographicCitation.volume |
18 |
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dc.bibliographicCitation.firstPage |
1 |
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dc.description.version |
acceptedVersion |
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tib.accessRights |
frei zug�nglich |
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