A roadmap for PERC cell efficiency towards 22%, focused on technology-related constraints

Abstract

Presently, the crystalline silicon (c-Si) photovoltaic (PV) industry is switching from standard cells to PERC cells to increase cell efficiency from about 18% to about 20%. This paper gives a roadmap for increasing PERC cell efficiency further towards 22%. Which equipment and which process conditions are feasible to go beyond 20% efficiency? To help answer this as generally as possible, we conduct state-of-the-art modelling in which we sweep the inputs that represent major technology-related constraints, such as diffusion depth, metal finger width and height, alignment tolerances, etc. (these are assigned to the x- And y-axes of our graphs). We then predict the optimum device parameters resulting from these restrictions (shown as contour lines). There are many different ways to achieve 22%. Our modelling predicts, for example, that 60 μm wide screen-printed metal fingers are sufficiently narrow if the alignment tolerance (width of the n++ region) is below 90 μm. The rear may be contacted with 30 μm wide openings of the Al2O3/SiNx stack and with local J0,BSF values as high as 900 fA/cm2. If these requirements cannot be met, they may be compensated by improvements in other device parts. Regardless of this, the wafer material requires a SRH lifetime of at least 1 ms at excess carrier densities near 10(14) cm(-3).